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  • CONFERENCE PAPER
    Ahmadi N, Constandinou TG, Bouganis C, 2018,

    Spike rate estimation using Bayesian Adaptive Kernel Smoother (BAKS) and its application to brain machine interfaces

    , 40th International Conference of the IEEE Engineering in Medicine and Biology Society (EMBC), Publisher: IEEE

    Brain Machine Interfaces (BMIs) mostly utilise spike rate as an input feature for decoding a desired motor output as it conveys a useful measure to the underlying neuronal activity. The spike rate is typically estimated by a using non-overlap binning method that yields a coarse estimate. There exist several methods that can produce a smooth estimate which could potentially improve the decoding performance. However, these methods are relatively computationally heavy for real-time BMIs. To address this issue, we propose a new method for estimating spike rate that is able to yield a smooth estimate and also amenable to real-time BMIs. The proposed method, referred to as Bayesian adaptive kernel smoother (BAKS), employs kernel smoothing technique that considers the bandwidth as a random variable with prior distribution which is adaptively updated through a Bayesian framework. With appropriate selection of prior distribution and kernel function, an analytical expression can be achieved for the kernel bandwidth. We apply BAKS and evaluate its impact on of fline BMI decoding performance using Kalman filter. The results show that overlap BAKS improved the decoding performance up to 3.33% and 12.93% compared to overlap and non-overlapbinning methods, respectively, depending on the window size. This suggests the feasibility and the potential use of BAKS method for real-time BMIs.

  • JOURNAL ARTICLE
    Liu Y, Pereira JL, Constandinou TG, 2018,

    Event-driven processing for hardware-efficient neural spike sorting

    , JOURNAL OF NEURAL ENGINEERING, Vol: 15, ISSN: 1741-2560
  • JOURNAL ARTICLE
    Luan S, Williams I, Maslik M, Liu Y, De Carvalho F, Jackson A, Quiroga RQ, Constandinou TGet al., 2018,

    Compact standalone platform for neural recording with real-time spike sorting and data logging.

    , J Neural Eng, Vol: 15

    OBJECTIVE: Longitudinal observation of single unit neural activity from large numbers of cortical neurons in awake and mobile animals is often a vital step in studying neural network behaviour and towards the prospect of building effective brain-machine interfaces (BMIs). These recordings generate enormous amounts of data for transmission and storage, and typically require offline processing to tease out the behaviour of individual neurons. Our aim was to create a compact system capable of: (1) reducing the data bandwidth by circa 2 to 3 orders of magnitude (greatly improving battery lifetime and enabling low power wireless transmission in future versions); (2) producing real-time, low-latency, spike sorted data; and (3) long term untethered operation. APPROACH: We have developed a headstage that operates in two phases. In the short training phase a computer is attached and classic spike sorting is performed to generate templates. In the second phase the system is untethered and performs template matching to create an event driven spike output that is logged to a micro-SD card. To enable validation the system is capable of logging the high bandwidth raw neural signal data as well as the spike sorted data. MAIN RESULTS: The system can successfully record 32 channels of raw neural signal data and/or spike sorted events for well over 24 h at a time and is robust to power dropouts during battery changes as well as SD card replacement. A 24 h initial recording in a non-human primate M1 showed consistent spike shapes with the expected changes in neural activity during awake behaviour and sleep cycles. SIGNIFICANCE: The presented platform allows neural activity to be unobtrusively monitored and processed in real-time in freely behaving untethered animals-revealing insights that are not attainable through scheduled recording sessions. This system achieves the lowest power per channel to date and provides a robust, low-latency, low-bandwidth and verifiable outp

  • JOURNAL ARTICLE
    Maslik M, Liu Y, Lande TS, Constandinou TGet al., 2018,

    Continuous-Time Acquisition of Biosignals Using a Charge-Based ADC Topology

    , IEEE TRANSACTIONS ON BIOMEDICAL CIRCUITS AND SYSTEMS, Vol: 12, Pages: 471-482, ISSN: 1932-4545
  • CONFERENCE PAPER
    Rapeaux A, Brunton E, Nazarpour K, Constandinou TGet al., 2018,

    Preliminary study of time to recovery of rat sciatic nerve from high frequency alternating current nerve block

    , 40th International Conference of the IEEE Engineering in Medicine and Biology Society (EMBC), Publisher: IEEE

    High-Frequency alternating current nerve block has great potential for neuromodulation-based therapies. However, no precise measurements have been made of the time needed for nerves to recover from block once the signal has been turned off. This study aims to characterise time to recoveryof the rat sciatic nerve after 30 seconds of block at varying amplitudes and frequencies. Experiments were carried out in-vivo to quantify recovery times and recovery completeness within 0.7s from the end of block. The sciatic nerve was blocked with an alternating square wave signal of amplitudeand frequency ranging from 2 to 9mA and 10 to 50 kHz respectively. To determine the recovery dynamics the nerve was stimulated at 100 Hz after cessation of the blocking stimulus. Electromyogram signals were measured from the gastrocnemius medialis and tibialis anterior muscles during trials as indicators of nerve function. This allowed for nerve recovery to bemeasured with a resolution of 10 ms. This resolution is much greater than previous measurements of nerve recovery in the literature. Times for the nerve to recover to a steady state of activity ranged from 20 to 430 milliseconds and final relative recovery activity at 0.7 seconds spanned 0.2 to 1 approximately. Higher blocking signal amplitudes increased recovery time and decreased recovery completeness. These results suggestthat blocking signal properties affect nerve recovery dynamics, which could help improve neuromodulation therapies and allow more precise comparison of results across studies using different blocking signal parameters.

  • CONFERENCE PAPER
    Szostak KM, Constandinou TG, 2018,

    Hermetic packaging for implantable microsystems: effectiveness of sequentially electroplated AuSn alloy

    , 40th International Conference of the IEEE Engineering in Medicine and Biology Society (EMBC), Publisher: IEEE

    With modern microtechnology, there is an aggressive miniaturization of smart devices, despite an increasing level of integration and overall complexity. It is therefore becoming increasingly important to be achieve reliable, compact packaging. For implantable medical devices (IMDs), the package must additionally provide a high quality hermetic environmentto protect the device from the human body. For chip-scale devices, AuSn eutectic bonding offers the possibility of forming compact seals that achieve ultra-low permeability. A key feature is this can be achieved at process temperatures of below 350 C, therefore allowing for the integration of sensors and microsystems with CMOS electronics within a single package. Issueshowever such as solder wetting, void formation and controlling composition make formation of high-quality repeatable seals highly challenging. Towards this aim, this paper presents our experimental work characterizing the eutectic stack deposition. We detail our design methods and process flow, share our experiences in controlling electrochemical deposition of AuSnalloy and finally discuss usability of sequential electroplating process for the formation of hermetic eutectic bonds.

  • BOOK CHAPTER
    Williams I, Leene L, Constandinou TG, 2018,

    Next Generation Neural Interface Electronics

    , Circuit Design Considerations for Implantable Devices, Editors: Cong, Publisher: River Publishers, Pages: 141-178, ISBN: 978-87-93519-86-2
  • CONFERENCE PAPER
    Davila-Montero S, Barsakcioglu DY, Jackson A, Constandinou TG, Mason AJet al., 2017,

    Real-time Clustering Algorithm that Adapts to Dynamic Changes in Neural Recordings

    , IEEE International Symposium on Circuits and Systems (ISCAS), Publisher: IEEE, Pages: 690-693, ISSN: 0271-4302
  • CONFERENCE PAPER
    De Marcellis A, Palange E, Faccio M, Stanchieri GDP, Constandinou TGet al., 2017,

    A 250Mbps 24pJ/bit UWB-inspired Optical Communication System for Bioimplants

    , Turin, Italy, IEEE Biomedical Circuits and Systems (BioCAS) Conference, Pages: 132-135
  • CONFERENCE PAPER
    Feng P, Constandinou TG, Yeon P, Ghovanloo Met al., 2017,

    Millimeter-Scale Integrated and Wirewound Coils for Powering Implantable Neural Microsystems

    , IEEE Biomedical Circuits and Systems (BioCAS) Conference, Pages: 488-491
  • CONFERENCE PAPER
    Gao C, Ghoreishizadeh S, Liu Y, Constandinou Tet al., 2017,

    On-chip ID Generation for Multi-node Implantable Devices using SA-PUF

    , IEEE International Symposium on Circuits and Systems (ISCAS), Publisher: IEEE, Pages: 678-681, ISSN: 0271-4302
  • CONFERENCE PAPER
    Ghoreishizadeh SS, Haci D, Liu Y, Constandinou TGet al., 2017,

    A 4-Wire Interface SoC for Shared Multi- Implant Power Transfer and Full-duplex Communication

    , 8th IEEE Latin American Symposium on Circuits & Systems (LASCAS), Publisher: IEEE
  • JOURNAL ARTICLE
    Ghoreishizadeh SS, Haci D, Liu Y, Donaldson N, Constandinou TGet al., 2017,

    Four-Wire Interface ASIC for a Multi-Implant Link

    , IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS, Vol: 64, Pages: 3056-3067, ISSN: 1549-8328
  • CONFERENCE PAPER
    Guven O, Eftekhar A, Kindt W, Constandinou TGet al., 2017,

    Low-Power Real-Time ECG Baseline Wander Removal: Hardware Implementation

    , IEEE International Symposium on Circuits and Systems (ISCAS), Publisher: IEEE, ISSN: 0271-4302
  • CONFERENCE PAPER
    Haci D, Liu Y, Constandinou TG, 2017,

    32-Channel Ultra-Low-Noise Arbitrary Signal Generation Platform for Biopotential Emulation

    , IEEE International Symposium on Circuits and Systems (ISCAS), Publisher: IEEE, Pages: 698-701, ISSN: 0271-4302
  • CONFERENCE PAPER
    Leene LB, Constandinou TG, 2017,

    A 0.5V Time-Domain Instrumentation Circuit with Clocked and Unclocked Delta Sigma Operation

    , IEEE International Symposium on Circuits and Systems (ISCAS), Publisher: IEEE, Pages: 2619-2622, ISSN: 0271-4302
  • JOURNAL ARTICLE
    Leene LB, Constandinou TG, 2017,

    A 0.016 mm(2) 12b Delta Sigma SAR With 14 fJ/conv. for Ultra Low Power Biosensor Arrays

    , IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS, Vol: 64, Pages: 2655-2665, ISSN: 1549-8328
  • JOURNAL ARTICLE
    Leene LB, Constandinou TG, 2017,

    Time Domain Processing Techniques Using Ring Oscillator-Based Filter Structures

    , IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS, Vol: 64, Pages: 3003-3012, ISSN: 1549-8328
  • JOURNAL ARTICLE
    Liu Y, Luan S, Williams I, Rapeaux A, Constandinou TGet al., 2017,

    A 64-Channel Versatile Neural Recording SoC with Activity Dependant Data Throughput

    , IEEE Transactions on Biomedical Circuits and Systems, Vol: 11, Pages: 1344-1355, ISSN: 1932-4545

    Modern microtechnology is enabling the channel count of neural recording integrated circuits to scale exponentially. However, the raw data bandwidth of these systems is increasing proportionately, presenting major challenges in terms of power consumption and data transmission (especially for wireless systems). This paper presents a system that exploits the sparse nature of neural signals to address these challenges and provides a reconfigurable low-bandwidth event-driven output. Specifically, we present a novel 64-channel low noise (2.1μVrms, low power (23μW per analogue channel) neural recording system-on-chip (SoC). This features individually-configurable channels, 10-bit analogue-to-digital conversion, digital filtering, spike detection, and an event-driven output. Each channel's gain, bandwidth & sampling rate settings can be independently configured to extract Local Field Potentials (LFPs) at a low data-rate and/or Action Potentials (APs) at a higher data rate. The sampled data is streamed through an SRAM buffer that supports additional on-chip processing such as digital filtering and spike detection. Real-time spike detection can achieve ~2 orders of magnitude data reduction, by using a dual polarity simple threshold to enable an event driven output for neural spikes (16-sample window). The SoC additionally features a latency-encoded asynchronous output that is critical if used as part of a closed-loop system. This has been specifically developed to complement a separate on-node spike sorting co-processor to provide a real-time (low latency) output. The system has been implemented in a commercially-available 0.35μm CMOS technology occupying a silicon area of 19.1mm² (0.3mm² gross per channel), demonstrating a low power & efficient architecture which could be further optimised by aggressive technology and supply voltage scaling.

  • CONFERENCE PAPER
    Luo J, Firfilionis D, Ramezani R, Dehkhoda F, Soltan A, Degenaar P, Liu Y, Constandinou TGet al., 2017,

    Live demonstration: a closed-loop cortical brain implant for optogenetic curing epilepsy

    , IEEE Biomedical Circuits and Systems (BioCAS) Conference, Publisher: IEEE, Pages: 169-169

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